The present invention relates to improved techniques for facilitating the transmission of data among disparate communication networks. More particularly, the present invention relates to improved devices and methods for facilitating transmission of packet data traffic and ATM data traffic on a single communication link.
With the information revolution and particularly with the rise of the Internet and the voice/data/video convergence, the volume of data to be sent and received over various communication networks have increased exponentially in recent years. Data, as the term is utilized in the present invention, relates to digital data that may be employed to carry voice, video, or any other information (such as text, graphics, and the like) that can be represented as a digital signal. To cope with the exponential increase in the amount of data being transmitted and received, network technologies have evolved as well. Nowadays, two dominant network technologies have emerged: packet-based technology and asynchronous transfer mode-based (ATM) technology. Packet technology includes TCP/IP, token ring, etc,. One example of packet technology is IP (Internet Protocol) packets transmitted over OSI layer 2. Another example of packet technology is Ethernet. ATM technology is well known and well defined and will not be elaborated further here.
For a while, it appears that ATM may be the dominant technology for future communication networks. Accordingly, many businesses spent heavily to convert their existing networks to ATM technology. The emergence of the Internet has caused many to rethink their network strategy, and nowadays, many believe that packet-based technologies represent the wave of the future. Accordingly, some of the earlier adopters of ATM technology, as well as new customers, have chosen packet-based technology as their preferred networking technology. As a result, the customer base currently employs both ATM technologies and packet-based technologies. For data communication among these customers to take place seamlessly, a translation device is required.
In the prior art, one of the devices that translates between ATM data and packet data is generally known as a segmentation-and-reassembly (SAR) engine. The SAR engine typically resides at a location in the network where data from different customers and/or subnetworks is switched. FIG. 1A illustrates an Internet service provider 100, representing one such location in the current network where SAR engines may be found. Referring now to FIG. 1A, a portion of the communication network for allowing Internet users 102 to access the Internet 104 is shown. For the purpose of the present example, Internet users 102 are shown accessing the Internet through either phone lines 106 or DSL (Digital Subscriber Lines) 108, although other access technologies may also be utilized with the present invention.
In the case of phone lines 106, the user typically achieves Internet access through a dial-up connection. Multiple dial-up connections are aggregated at a circuit switch 110, which time-division multiplexes data from a plurality of dial-up connections into a (TDM) time-division-multiplexed stream to be transmitted via a TDM link 112. The TDM link 112 is terminated at a modem bank 114, which converts the TDM data into packet data for transmission through a wide area network packet link, such as frame relay link 115.
As shown in FIG. 1A, frame relay link 115 terminates at an access router 140, which routes data from multiple frame relay links onto an internal packet link, such as an Ethernet link 142. Ethernet link 142 represents the internal local connection within ISP 100, which interconnects among its server computers (not shown to simplify the illustration). Ethernet link 142 connects with a backbone router 144 as shown, which then routes the data received from the Ethernet link(s) to either a backbone packet link 146 (which may be, for example, packet over SONET or packet over DWDM) or a backbone ATM link 148 for transmission out to Internet 104. One skilled in the art should readily appreciate that the aforementioned steps are reversed when data destined for a user on one of dial-up connections 106 is received at ISP 100 from the Internet 104 through either backbone ATM link 148 or backbone packet link 146.
In the case of DSL lines 108, the individual DSL lines are terminated at a DSL Access Multiplexer 116, which combines the DSL data from a plurality of DSL channels into an ATM stream to be transmitted via an ATM link 118 to an ATM switch 120. ATM switch 120 multiplexes data from various ATM links 118 for transmission via a wide area network ATM link such as ATM link 122. As in the case of frame relay link 115, ATM link 122 also couples to an access router of ISP 100, shown in FIG. 1A as access router 160. However, because the packet-oriented protocol on Ethernet link 162 internal to ISP 100 is different from the ATM protocol on ATM link 122, a translation device is necessary. That translation device is shown in FIG. 1A as the segmentation-and-reassembly (SAR) engine 164. SAR 164 will be discussed in greater detail in FIG. 3 below.
Once the data on ATM link 122 is translated into packet-oriented data and routed to backbone router 144 (via Ethernet link 162 and the server computers of ISP 100), the data is then routed by backbone router 144 to either a backbone packet link 146 or a backbone ATM link 148 for transmission out to Internet 104. In the case wherein data is routed to ATM link 148 from ISP 100, the packet-oriented data is translated via a SAR 170 to ATM cells. One skilled in the art should readily appreciate that the aforementioned steps are reversed when data destined for a user on one of DSL connections 108 is received at ISP 100 from the Internet 104 through either backbone ATM link 148 or backbone packet link 146.
As seen in FIG. 1A, two physical backbone links (comprising at least four separate optical fibers since each optical fiber carries information in only a single direction) are required to allow ISP 100 to handle both ATM traffic and packet-oriented traffic. At the cost of tens of thousands of dollars to purchase and/or lease each optical fiber to implement each backbone link (such as backbone packet link 146 or backbone ATM link 148), this arrangement imposes a high economic burden on ISP operators and other network operators. The high cost for these separate optical links are also hard to justify in view of technologies such as dense wave division multiplex (DWDM), which allows an existing optical fiber to carry much more data per optical fiber than possible previously. Thus, some ISP may find that they still need to bear the economic burden of paying for two fibers in each direction in order to accommodate both ATM traffic and packet-oriented traffic when neither fiber may be employed at anywhere near their full bandwidth capacity.
In the prior art, one of the backbone links may be eliminated through the use of a SONET (synchronous optical network) multiplexer. As shown in FIG. 1B, a SONET multiplexer 192 is located at the Internet-side of ISP 100 and is coupled to both backbone packet link 106 and backbone ATM link 148 on the ISP side. On the Internet-side of SONET multiplexer 192, a single optical channel may be employed to transport both packet-oriented data and ATM data. However, a SONET multiplexer is an expensive and complex electronic system, costing upwards of fifty thousand dollars ($50,000) or more in some cases and increasing the maintenance burden on the operators. Thus, although the use of a SONET multiplexer theoretically allows ISP operators to avoid paying for separate backbone links to connect to the Internet to accommodate ATM data and packet data, many ISP operators find that the high acquisition cost and additional maintenance burden of the SONET multiplexer makes its purchase difficult to justify.
In view of the foregoing, there are desired improved devices and methods for facilitating transmission of packet data traffic and ATM data traffic on a single communication link.
The present invention relates to a combined ATM/packet transmission architecture configured for coupling with a mixed data optical fiber carrying both ATM cells and data packets in a time-division multiplexed manner. The combined ATM/packet transmission architecture includes a transmission convergence device (TCD) circuit having a first TCD input port configured to receive first ATM cells and first data packets from the optical fiber. The TCD circuit has a first TCD output bus configured to output second ATM cells and second data packets from the TCD circuit. The second ATM cells and the second data packets include information from the first ATM cells and the first data packets. The combined ATM/packet transmission architecture includes a combined ATM/packet segmentation-and-reassembly (SAR) circuit having a first SAR input bus configured to be coupled to the first TCD output bus of the TCD circuit to receive the second ATM cells and the second data packets, wherein the combined ATM/packet SAR circuit includes a first SAR output port configured to output first mixed data packets from the combined ATM/packet SAR circuit, the first mixed data packets include information from both the second ATM cells and the second data packets.
The invention relates, in one embodiment, to a processor-based architecture having a processor for facilitating transmission between an ATM port, a first packet port, and a second packet port. The processor-based architecture includes random access memory and a processor coupled to the random access memory and configured to receive ATM cells from the ATM port and first packets from the first packet port and for outputting second packets containing information from both the ATM cells and the first packets on the second packet port. The processor-based architecture includes segmentation-and-reassembly to facilitate bi-directional packet-to-ATM translation functionality. In one embodiment, the processor-based architecture is implemented on a single card.
In another embodiment, the invention relates to a segmentation-and-reassembly engine, which includes a bus interface for receiving both ATM cells and first packets. The segmentation-and-reassembly engine includes first interface logic block for receiving the ATM cells and the first packets from the bus interface and for segregating the ATM cells from the first packets. The segmentation-and-reassembly engine further includes a second interface logic block coupled to the first interface logic block for receiving the first packets from the first interface logic block to output the first packets. There is further included a reassembly engine coupled to the first interface logic block for receiving the ATM cells and for reassembling the ATM cells into second packets. There is also included a buffer circuit coupled to the reassembly engine and the second interface logic block, the buffer circuit being configured to buffer the second packets for output by the second interface logic block.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.